1. Field of the Invention
The present invention relates to a semiconductor device for electrostatic discharge protection of a high withstanding voltage semiconductor integrated circuit.
2. Description of the Related Art
In a semiconductor integrated circuit, an electrostatic discharge protection circuit is generally formed between an outer terminal and an inner circuit so as to prevent breakage of the inner circuit due to an overcurrent noise (for example, electrostatic discharge (ESD)) applied from the outer terminal or an overcurrent pulse which may be assumed by a latch-up test. For example, assuming a case where the overcurrent noise is applied to an I/O terminal, the electrostatic discharge protection circuit described above is designed to operate when the voltage applied to the I/O terminal becomes a voltage higher by a few volts than a maximum operating voltage of the semiconductor integrated circuit (hereinafter, referred to as trigger voltage), and to allow the overcurrent noise to flow into a ground terminal or a power supply terminal. The simplest method to achieve this object is to connect an element serving as an electrostatic discharge protection element between the I/O terminal and the ground terminal, the element having a characteristic which does not allow a current to flow until a certain voltage is applied but allows the current to rapidly flow after a voltage equal to or more than the certain voltage is applied, such as a diode (reverse connection), a metal oxide semiconductor (MOS) transistor having a gate in an off state, or a thyristor. A tolerance against the overcurrent noise of the semiconductor integrated circuit including such electrostatic discharge protection element described above may be evaluated using a simulator such as an ESD simulator or a latch-up simulator.
In a case where a semiconductor integrated circuit having a higher withstanding voltage is manufactured, the electrostatic discharge protection element used for protection is required to allow the overcurrent noise to flow into the ground terminal or the power supply terminal at a higher trigger voltage. Accordingly, the electrostatic discharge protection element is required to be an element stronger against breakage due to Joule heat. In addition, concerning a pulse width of the overcurrent noise, condition with respect to the breakage due to the Joule heat becomes more severe as the pulse width becomes longer in time. In particular, the pulse width of the overcurrent noise used in the latch-up test is of the order of few ms, which is longer in time compared with other noises. Accordingly, it is particularly necessary to pay attention to breakage of the electrostatic discharge protection element itself.
In order to prevent breakage of the electrostatic discharge protection element itself due to the Joule heat, decrease of current density per unit area of a section in which a current is applied is required to suppress heat generation. However, this increases the element in size, and the size may not be unlimitedly increased in view of cost. Further, the method for protection may differ according to a state of each terminal when the overcurrent noise is applied. For example, in a case of the ESD, the noise is applied under a state in which terminals other than the terminal to which the noise is applied and the ground terminal are in an open state, and hence the ground terminal is the only terminal for releasing the noise. However, in a case of the overcurrent noise of the latch-up test, the overcurrent noise is applied to the remaining terminals under a state in which the power supply terminal and the ground terminal are in an electricity state, and hence terminals for releasing the overcurrent noise may be two, that is, the power supply terminal and the ground terminal.
Protection circuits such as circuits described in a first conventional example (FIG. 4) and a second conventional example (FIG. 5) have been conceived as a method capable of protecting the inner circuit from the overcurrent noise having a pulse width of the order of few ms, such as the overcurrent noise of the ESD and the test pulse of the latch-up simulator, in a case where the inner circuit having a higher withstanding voltage is protected as described above, without increasing the chip size (for example, see Japanese Patent Application Laid-open No. 2005-72607).
The first conventional example (FIG. 4) describes a protection circuit including a protection diode 5 connected between an I/O terminal 2 and a ground terminal 3, for protection against the overcurrent noise of the ESD, and a protection diode 4 connected between a power supply terminal 1 and the I/O terminal 2, for protection against the overcurrent noise of the latch-up test. For example, when the overcurrent noise of the ESD is applied to the I/O terminal 2, because the power supply terminal 1 is not connected, breakdown of the protection diode 5 connected between the I/O terminal 2 and the ground terminal 3 occurs, and hence the overcurrent noise may be released to the ground terminal 3. In the case of the latch-up test, the power supply terminal 1 is connected to a power source and a potential is maintained to the maximum operating voltage. For example, when the overcurrent noise is applied to the I/O terminal 2 in this state, the overcurrent noise flows through the protection diode 4 connected between the I/O terminal 2 and the power supply terminal 1 when the potential of the I/O terminal 2 becomes equal to or more than (potential of the power supply terminal 1+diffusion potential of the protection diode 4), and then flows into the power supply terminal 1 in a forward direction.
The second conventional example (FIG. 5) describes a protection circuit including an off MOS type field effect transistor 10 connected between an I/O terminal 7 and a ground terminal 8, for protection against the overcurrent noise of the ESD, and a protection diode 9 connected between a power supply terminal 6 and the I/O terminal 7, for protection against the overcurrent noise of the latch-up test. For example, when the overcurrent noise of the ESD is applied to the I/O terminal 7, because the power supply terminal 6 is not connected, breakdown of the MOS type field effect transistor 10 having a gate in an off state and connected between the I/O terminal 7 and the ground terminal 8 occurs, and hence the overcurrent noise may be released to the ground terminal 8. In the case of the latch-up test, the power supply terminal 6 is connected to the power source and the potential is maintained to the maximum operating voltage. For example, when the overcurrent noise is applied to the I/O terminal 7 in this state, the overcurrent noise flows through the protection diode 9 connected between the I/O terminal 7 and the power supply terminal 6 when the potential of the I/O terminal 7 becomes equal to or more than (potential of the power supply terminal 6+diffusion potential of the protection diode 9), and then flows into the power supply terminal 6 in a forward direction.
It is necessary to take into consideration that, in a case where the electrostatic discharge protection circuits as described in the conventional examples are actually manufactured, when the overcurrent noise is applied to the electrostatic discharge protection element, electrons and holes are generated due to the overcurrent noise, and thus there is a possibility to turn on a parasitic bipolar transistor formed between internal elements. As a method of absorbing the electrons and the holes generated due to the overcurrent noise and suppressing diffusion thereof into the inner circuit to prevent turning on the parasitic bipolar transistor formed between the internal elements, it is conceivable to surround the periphery of the protection element by two rings, that is, for example, a diffusion region (hereinafter, referred to as guard ring) having an opposite conductivity type to that of the substrate, which is connected to the power supply terminal and has a fixed potential, and a guard ring having the same conductivity type as the substrate, which is connected to the ground terminal and has a fixed potential.
When the electrostatic discharge protection circuits as described in the conventional examples are actually manufactured, a configuration thereof is as illustrated in FIG. 6. A protection element 100 has the following configuration. For example, in a p-type semiconductor substrate, for example, an n-channel type MOS transistor 19 having a gate in an off state is formed as an ESD protection element for protection against the overcurrent noise of the ESD. A drain of the re-channel type MOS transistor 19 is connected to the power supply terminal and each of a source, a gate, and a backgate thereof is connected to the ground terminal. In the periphery of the n-channel type MOS transistor 19, for example, a p-type well 13 serving as a guard ring having the same conductivity type as the substrate is formed, and further, for example, a p-type high concentration region 14 for contacting to the ground terminal is formed. Further, on an outer side thereof, for example, an n-type well 11 as a guard ring having an opposite conductivity type to that of the substrate is formed, and further, for example, an n-type high concentration region 12 for contacting to the ground terminal is formed. In addition, an electrostatic discharge protection circuit device 101 has the following configuration. As a latch-up protection diode for protection against the overcurrent noise of the latch-up test, a latch-up protection diode 18 having, for example, an anode corresponding to a p-type high concentration region 17 and, for example, a cathode corresponding to an n-type well 15 and an n-type high concentration region 16 is formed. The anode is connected to the I/O terminal, and the cathode is connected to the power supply terminal. In the periphery of the latch-up protection diode 18, for example, the p-type well 13 serving as a guard ring having the same conductivity type is formed, and further, for example, the p-type high concentration region 14 for contacting to the ground terminal is formed. Further, on the outer side thereof, for example, the n-type well 11 as a guard ring having the opposite conductivity type to that of the substrate is formed, and further, for example, the n-type high concentration region 12 for contacting to the ground terminal is formed.
When the electrostatic discharge protection circuits as described in the conventional examples are manufactured, there require two protection elements, that is, the n-channel MOS type field effect transistor 19 having a gate in an off state for protection against the overcurrent noise of the ESD and the latch-up protection diode 18 for protection against the overcurrent noise of the latch-up test. Each of the elements is required to be surrounded by the p-type well (guard ring) 13 having the same conductivity type as the substrate and the n-type well (guard ring) 11 having the opposite conductivity type to that of the substrate, leading to a problem in that the chip is increased in size.